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Old 01-09-2022, 08:46 AM   #1
sndwvs
Senior Member
 
Registered: Aug 2014
Posts: 1,915

Rep: Reputation: Disabled
Rock 5 RK3588 (aarch64)


information board:

ROCK 5 Model B
Specifications:
  • SoC – Rockchip RK3588 octa-core processor with four Cortex-A76 cores @ 2.4 GHz, four Cortex-A55 cores @ 1.8 GHz, an Ar, Mali G610MC4 GPU, a 6TOPS NPU, 8K 10-bit decoder, 8K encoder
  • System Memory – 4GB, 8GB, or 16GB LPDDR4x
  • Storage
    M.2 2280 socket for NVMe SSD (PCIe 3.0 x4) up to 2,000 MB/s
    MicroSD card socket
    eMMC flash socket
  • Video Output
    2x HDMI 2.1 up to 8Kp60
    1x USB-C via DisplayPort alt. mode up to 8Kp30
    Three independent displays supported
  • Video Input
    1x micro HDMI input up to 4Kp60
    2x MIPI CSI connectors
  • Networking
    2.5 Gbps Ethernet RJ45 port with PoE support
    Support for WiFi 6E and Bluetooth 5.2 M.2 module
  • USB – 2x USB 3.0 Type-A ports, 1x USB 3.0 Type-C port, 2x USB 2.0 ports
  • Expansion – 40-pin GPIO header
  • Dimensions – 100 x 72mm (Pico-ITX form factor)
Attached Thumbnails
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Old 05-02-2023, 02:37 PM   #5
sndwvs
Senior Member
 
Registered: Aug 2014
Posts: 1,915

Original Poster
Rep: Reputation: Disabled
installation README.TXT
kernel 5.10.110

slarm64-current-aarch64-core-rock_5-5.10.110-build-20230502.img.zst
slarm64-current-aarch64-core-rock_5-5.10.110-build-20230502.img.zst.sha256
slarm64-current-aarch64-server-rock_5-5.10.110-build-20230502.img.zst
slarm64-current-aarch64-server-rock_5-5.10.110-build-20230502.img.zst.sha256
slarm64-current-aarch64-xfce-rock_5-5.10.110-build-20230502.img.zst
slarm64-current-aarch64-xfce-rock_5-5.10.110-build-20230502.img.zst.sha256

Code:
DDR Version V1.08 20220617
LPDDR4X, 2112MHz
channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=4096MB
channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=4096MB
channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=4096MB
channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=4096MB
Manufacturer ID:0xff 
CH0 RX Vref:26.7%, TX Vref:22.8%,22.8%
CH1 RX Vref:29.7%, TX Vref:21.8%,21.8%
CH2 RX Vref:24.7%, TX Vref:24.8%,23.8%
CH3 RX Vref:28.7%, TX Vref:23.8%,23.8%
change to F1: 528MHz
change to F2: 1068MHz
change to F3: 1560MHz
change to F0: 2112MHz
out
U-Boot SPL board init
U-Boot SPL 2017.09-rk3588 (May 02 2023 - 21:59:05)
Trying to boot from MMC1
Trying fit image at 0x4000 sector
## Verified-boot: 0
## Checking atf-1 0x00040000 ... sha256(bb1bbbc832...) + OK
## Checking uboot 0x00200000 ... sha256(375d6e529a...) + OK
## Checking fdt 0x00311908 ... sha256(83adf972b8...) + OK
## Checking atf-2 0x000f0000 ... sha256(30812190d0...) + OK
## Checking atf-3 0xff100000 ... sha256(cb7bdbec2b...) + OK
Jumping to U-Boot(0x00200000) via ARM Trusted Firmware(0x00040000)
Total: 584.47 ms

INFO:    Preloader serial: 2
NOTICE:  BL31: v2.3():v2.3-499-ge63a16361:derrick.huang
NOTICE:  BL31: Built : 10:58:38, Jan 10 2023
INFO:    spec: 0x1
INFO:    ext 32k is not valid
INFO:    ddr: stride-en 4CH
INFO:    GICv3 without legacy support detected.
INFO:    ARM GICv3 driver initialized in EL3
INFO:    valid_cpu_msk=0xff bcore0_rst = 0x0, bcore1_rst = 0x0
INFO:    system boots from cpu-hwid-0
INFO:    idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
INFO:    dfs DDR fsp_params[0].freq_mhz= 2112MHz
INFO:    dfs DDR fsp_params[1].freq_mhz= 528MHz
INFO:    dfs DDR fsp_params[2].freq_mhz= 1068MHz
INFO:    dfs DDR fsp_params[3].freq_mhz= 1560MHz
INFO:    BL31: Initialising Exception Handling Framework
INFO:    BL31: Initializing runtime services
WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
ERROR:   Error initializing runtime service opteed_fast
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0x200000
INFO:    SPSR = 0x3c9


U-Boot 2017.09-rk3588 (May 02 2023 - 22:00:59 +0300)

Model: Radxa ROCK 5B
PreSerial: 2, raw, 0xfeb50000
DRAM:  15.7 GiB
Sysmem: init
Relocation Offset: eda65000
Relocation fdt: eb9f95d8 - eb9fecd0
CR: M/C/I
Using default environment

mmc@fe2c0000: 0, mmc@fe2e0000: 1
Bootdev(atags): mmc 0
MMC0: Legacy, 52Mhz
PartType: EFI
DM: v1
boot mode: normal
Model: Radxa ROCK 5B
CLK: (sync kernel. arm: enter 1008000 KHz, init 1008000 KHz, kernel 0N/A)
  b0pll 24000 KHz
  b1pll 24000 KHz
  lpll 24000 KHz
  v0pll 24000 KHz
  aupll 24000 KHz
  cpll 1500000 KHz
  gpll 1188000 KHz
  npll 24000 KHz
  ppll 1100000 KHz
  aclk_center_root 702000 KHz
  pclk_center_root 100000 KHz
  hclk_center_root 396000 KHz
  aclk_center_low_root 500000 KHz
  aclk_top_root 750000 KHz
  pclk_top_root 100000 KHz
  aclk_low_top_root 396000 KHz
Net:   No ethernet found.
Hit key to stop autoboot('CTRL+C'):  0 
switch to partitions #0, OK
mmc0 is current device
mmc@fe2c0000: 0 (SD)
mmc@fe2e0000: 1
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found U-Boot script /boot.scr
2604 bytes read in 10 ms (253.9 KiB/s)
## Executing script at 00500000
Boot script loaded from mmc 0
173 bytes read in 13 ms (12.7 KiB/s)
250246 bytes read in 127 ms (1.9 MiB/s)
30685696 bytes read in 15022 ms (1.9 MiB/s)
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
6397 bytes read in 86 ms (72.3 KiB/s)
Applying kernel provided DT overlay rockchip-rk3588-opp-oc-24ghz.dtbo
** File not found /dtb/rockchip/overlay/rockchip-fixup.scr **
17672258 bytes read in 8165 ms (2.1 MiB/s)
Fdt Ramdisk skip relocation
## Loading init Ramdisk from Legacy Image at 0a200000 ...
   Image Name:   uInitrd
   Image Type:   AArch64 Linux RAMDisk Image (gzip compressed)
   Data Size:    17672194 Bytes = 16.9 MiB
   Load Address: 00000000
   Entry Point:  00000000
   Verifying Checksum ... OK
## Flattened Device Tree blob at 0x0a100000
   Booting using the fdt blob at 0x0a100000
   reserving fdt memory region: addr=a100000 size=a3000
  'reserved-memory' cma: addr=10000000 size=10000000
  'reserved-memory' ramoops@110000: addr=110000 size=f0000
   Using Device Tree in place at 000000000a100000, end 000000000a1a5fff
Adding bank: 0x00200000 - 0xf0000000 (size: 0xefe00000)
Adding bank: 0x100000000 - 0x3fc000000 (size: 0x2fc000000)
Adding bank: 0x3fc500000 - 0x3fff00000 (size: 0x03a00000)
Total: 23936.88 ms

Starting kernel ...

[   25.766532] fiq_debugger fiq_debugger.0: IRQ fiq not found
[   25.766545] fiq_debugger fiq_debugger.0: IRQ wakeup not found
[   25.766552] fiq_debugger_probe: could not install nmi irq handler
[   26.678841] mpp-iep2 fdbb0000.iep: allocate roi buffer failed
[   26.679327] rk-pcie fe170000.pcie: IRQ msi not found
[   26.679338] rk-pcie fe170000.pcie: Missing *config* reg space
[   26.679407] rk-pcie fe170000.pcie: Missing *config* reg space
[   26.679432] rk-pcie fe170000.pcie: invalid resource
[   26.690336] rk-pcie fe150000.pcie: IRQ msi not found
[   26.690369] rk-pcie fe150000.pcie: Missing *config* reg space
[   26.690497] rk-pcie fe150000.pcie: Missing *config* reg space
[   26.690534] rk-pcie fe150000.pcie: invalid resource
[   26.690613] mpp_rkvdec2 fdc38100.rkvdec-core: shared_niu_a is not found!
[   26.690622] rkvdec2_init:1008: No niu aclk reset resource define
[   26.690628] mpp_rkvdec2 fdc38100.rkvdec-core: shared_niu_h is not found!
[   26.690634] rkvdec2_init:1011: No niu hclk reset resource define
[   26.691281] mpp_rkvdec2 fdc48100.rkvdec-core: shared_niu_a is not found!
[   26.691288] rkvdec2_init:1008: No niu aclk reset resource define
[   26.691295] mpp_rkvdec2 fdc48100.rkvdec-core: shared_niu_h is not found!
[   26.691300] rkvdec2_init:1011: No niu hclk reset resource define
[   26.756070] rk806 spi2.0: no sleep-setting state
[   26.756087] rk806 spi2.0: no reset-setting pinctrl state
[   26.756094] rk806 spi2.0: no dvs-setting pinctrl state
[   27.088394] arm-scmi firmware:scmi: Failed. SCMI protocol 17 not active.
[   27.103427] debugfs: File 'Capture' in directory 'dapm' already present!
[   27.104444] rk-multicodecs es8316-sound: ASoC: Property 'rockchip,audio-routing' does not exist or its length is not even
[   27.719817] mmc1: delay init for 600 ms to enable UHS mode
[   27.721209] debugfs: File 'Left Hp mixer' in directory 'dapm' already present!
[   27.721257] debugfs: File 'Right Hp mixer' in directory 'dapm' already present!
[   27.721295] debugfs: File 'HPCP L' in directory 'dapm' already present!
[   27.721318] debugfs: File 'HPCP R' in directory 'dapm' already present!
[   27.721348] debugfs: File 'HPVOL L' in directory 'dapm' already present!
[   27.721370] debugfs: File 'HPVOL R' in directory 'dapm' already present!
[   27.768422] debugfs: Directory 'fb000000.gpu-mali' with parent 'vdd_gpu_s0' already present!
[   27.771562] rockchip-dmc dmc: failed to get vop bandwidth to dmc rate
[   27.771600] rockchip-dmc dmc: failed to get vop pn to msch rl
[   27.772693] rockchip-dmc dmc: could not find power_model node
[   27.780291] rk-pcie fe190000.pcie: IRQ msi not found
[   27.780319] rk-pcie fe190000.pcie: Missing *config* reg space
[   27.780426] rk-pcie fe190000.pcie: Missing *config* reg space
[   27.780447] rk-pcie fe190000.pcie: invalid resource
[   27.784324] RKNPU fdab0000.npu: can't request region for resource [mem 0xfdab0000-0xfdabffff]
[   27.784363] RKNPU fdab0000.npu: can't request region for resource [mem 0xfdac0000-0xfdacffff]
[   27.784386] RKNPU fdab0000.npu: can't request region for resource [mem 0xfdad0000-0xfdadffff]
[   27.788526] debugfs: Directory 'fdab0000.npu-rknpu' with parent 'vdd_npu_s0' already present!
[   27.810214] RKNPU fdab0000.npu: failed to find power_model node
[   27.810241] RKNPU fdab0000.npu: RKNPU: failed to initialize power model
[   27.810254] RKNPU fdab0000.npu: RKNPU: failed to get dynamic-coefficient
[   29.152386] rk_hdmirx fdee0000.hdmirx-controller: hdmirx_cancel_cpu_limit_freq freq qos nod add
[   31.355973] BUG: spinlock bad magic on CPU#5, udevd/468
[   31.356019]  lock: 0xffffffc012a29080, .magic: 00000000, .owner: <none>/-1, .owner_cpu: 0


=======================================================================

if you want to transfer the system to SDcard to internal memory (eMMC or NAND),
follow transfer-to-disk

=======================================================================

slarm64 GNU/Linux (ttyFIQ0)
Kernel 5.10.110 (aarch64)

rock-5 login:

Last edited by sndwvs; 05-02-2023 at 02:39 PM.
 
Old 05-13-2023, 08:49 AM   #6
sndwvs
Senior Member
 
Registered: Aug 2014
Posts: 1,915

Original Poster
Rep: Reputation: Disabled
installation README.TXT
kernel 5.10.110

slarm64-current-aarch64-core-rock_5-5.10.110-build-20230513.img.zst
slarm64-current-aarch64-core-rock_5-5.10.110-build-20230513.img.zst.sha256
slarm64-current-aarch64-server-rock_5-5.10.110-build-20230513.img.zst
slarm64-current-aarch64-server-rock_5-5.10.110-build-20230513.img.zst.sha256
slarm64-current-aarch64-xfce-rock_5-5.10.110-build-20230513.img.zst
slarm64-current-aarch64-xfce-rock_5-5.10.110-build-20230513.img.zst.sha256

Code:
[    26.581] (==) modeset(0): Depth 24, (==) framebuffer bpp 32
[    26.581] (==) modeset(0): RGB weight 888
[    26.581] (==) modeset(0): Default visual is TrueColor
[    26.581] (II) Loading sub module "glamoregl"
[    26.581] (II) LoadModule: "glamoregl"
[    26.581] (II) Loading /usr/lib64/xorg/modules/libglamoregl.so
[    26.599] (II) Module glamoregl: vendor="X.Org Foundation"
[    26.599]    compiled for 1.21.1.8, module version = 1.0.1
[    26.599]    ABI class: X.Org ANSI C Emulation, version 0.4
[    27.878] (II) modeset(0): glamor X acceleration enabled on Mali-G610 (Panfrost)
[    27.879] (II) modeset(0): glamor initialized
[    27.879] (==) modeset(0): VariableRefresh: disabled
[    27.879] (==) modeset(0): AsyncFlipSecondaries: disabled
[    27.879] (II) modeset(0): Output HDMI-1 has no monitor section
[    28.025] (II) modeset(0): Output HDMI-2 has no monitor section
[    28.026] (II) modeset(0): Output DP-1 has no monitor section
[    28.027] (II) modeset(0): EDID for output HDMI-1
[    28.169] (II) modeset(0): EDID for output HDMI-2
[    28.169] (II) modeset(0): Manufacturer: SAM  Model: f57  Serial#: 810834008
[    28.169] (II) modeset(0): Year: 2019  Week: 26
[    28.169] (II) modeset(0): EDID Version: 1.3
[    28.169] (II) modeset(0): Digital Display Input
[    28.169] (II) modeset(0): Max Image Size [cm]: horiz.: 60  vert.: 34
[    28.170] (II) modeset(0): Gamma: 2.20
[    28.170] (II) modeset(0): DPMS capabilities: Off
[    28.170] (II) modeset(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
[    28.170] (II) modeset(0): First detailed timing is preferred mode
[    28.170] (II) modeset(0): redX: 0.652 redY: 0.341   greenX: 0.320 greenY: 0.608
[    28.170] (II) modeset(0): blueX: 0.146 blueY: 0.065   whiteX: 0.313 whiteY: 0.329
video is played by
Code:
ffplay
and
Code:
mpv --vo=gpu
 
1 members found this post helpful.
Old 06-06-2023, 05:39 AM   #8
SCerovec
Senior Member
 
Registered: Oct 2006
Location: Cp6uja
Distribution: Slackware on x86 and arm
Posts: 2,474
Blog Entries: 2

Rep: Reputation: 981Reputation: 981Reputation: 981Reputation: 981Reputation: 981Reputation: 981Reputation: 981Reputation: 981
Code:
DDR Version V1.07 20220412
LPDDR4X, 2112MHz
channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=4096MB
channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=4096MB
channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=4096MB
channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=4096MB
change to F1: 528MHz
change to F2: 1068MHz
change to F3: 1560MHz
change to F0: 2112MHz
out
INFO:    Preloader serial: 2
NOTICE:  BL31: v2.3():v2.3-499-ge63a16361:derrick.huang
NOTICE:  BL31: Built : 10:58:38, Jan 10 2023
INFO:    spec: 0x1
INFO:    ext 32k is not valid
INFO:    ddr: stride-en 4CH
INFO:    GICv3 without legacy support detected.
INFO:    ARM GICv3 driver initialized in EL3
INFO:    valid_cpu_msk=0xff bcore0_rst = 0x0, bcore1_rst = 0x0
INFO:    system boots from cpu-hwid-0
INFO:    idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
INFO:    dfs DDR fsp_params[0].freq_mhz= 2112MHz
INFO:    dfs DDR fsp_params[1].freq_mhz= 528MHz
INFO:    dfs DDR fsp_params[2].freq_mhz= 1068MHz
INFO:    dfs DDR fsp_params[3].freq_mhz= 1560MHz
INFO:    BL31: Initialising Exception Handling Framework
INFO:    BL31: Initializing runtime services
WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
ERROR:   Error initializing runtime service opteed_fast
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0x200000
INFO:    SPSR = 0x3c9


U-Boot 2017.09-rk3588 (May 20 2023 - 10:56:47 +0300)

Model: Radxa ROCK 5B
PreSerial: 2, raw, 0xfeb50000
DRAM:  15.7 GiB
Sysmem: init
Relocation Offset: eda65000
Relocation fdt: eb9f9738 - eb9fecc8
CR: M/C/I
Using default environment

no mmc device at slot 1
Card did not respond to voltage select!
do_rkimg_test: dev_desc is NULL!
mmc@fe2c0000: 0, mmc@fe2e0000: 1
Card did not respond to voltage select!
I wonder is there a way to make the default script iterate thru mmc 0 and 1 before giving up?

I suspect the kernel/uboot is switching from 0 to 1 and back what is understood as a SD image and eMMC image?

Otherwise great work with porting the patches to the 6.3.3 kernel

Could You possibly point me to the sources of the uboot with all the applied patches so i could try fiddle with what blocks the boot?
 
Old 06-06-2023, 11:48 AM   #9
sndwvs
Senior Member
 
Registered: Aug 2014
Posts: 1,915

Original Poster
Rep: Reputation: Disabled
Quote:
Originally Posted by SCerovec View Post
Code:
DDR Version V1.07 20220412
LPDDR4X, 2112MHz
channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=4096MB
channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=4096MB
channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=4096MB
channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=4096MB
change to F1: 528MHz
change to F2: 1068MHz
change to F3: 1560MHz
change to F0: 2112MHz
out
INFO:    Preloader serial: 2
NOTICE:  BL31: v2.3():v2.3-499-ge63a16361:derrick.huang
NOTICE:  BL31: Built : 10:58:38, Jan 10 2023
INFO:    spec: 0x1
INFO:    ext 32k is not valid
INFO:    ddr: stride-en 4CH
INFO:    GICv3 without legacy support detected.
INFO:    ARM GICv3 driver initialized in EL3
INFO:    valid_cpu_msk=0xff bcore0_rst = 0x0, bcore1_rst = 0x0
INFO:    system boots from cpu-hwid-0
INFO:    idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
INFO:    dfs DDR fsp_params[0].freq_mhz= 2112MHz
INFO:    dfs DDR fsp_params[1].freq_mhz= 528MHz
INFO:    dfs DDR fsp_params[2].freq_mhz= 1068MHz
INFO:    dfs DDR fsp_params[3].freq_mhz= 1560MHz
INFO:    BL31: Initialising Exception Handling Framework
INFO:    BL31: Initializing runtime services
WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
ERROR:   Error initializing runtime service opteed_fast
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0x200000
INFO:    SPSR = 0x3c9


U-Boot 2017.09-rk3588 (May 20 2023 - 10:56:47 +0300)

Model: Radxa ROCK 5B
PreSerial: 2, raw, 0xfeb50000
DRAM:  15.7 GiB
Sysmem: init
Relocation Offset: eda65000
Relocation fdt: eb9f9738 - eb9fecc8
CR: M/C/I
Using default environment

no mmc device at slot 1
Card did not respond to voltage select!
do_rkimg_test: dev_desc is NULL!
mmc@fe2c0000: 0, mmc@fe2e0000: 1
Card did not respond to voltage select!
I wonder is there a way to make the default script iterate thru mmc 0 and 1 before giving up?

I suspect the kernel/uboot is switching from 0 to 1 and back what is understood as a SD image and eMMC image?

Otherwise great work with porting the patches to the 6.3.3 kernel

Could You possibly point me to the sources of the uboot with all the applied patches so i could try fiddle with what blocks the boot?
my board is out of order, so there is no way to test.
source u-boot patches
 
1 members found this post helpful.
Old 06-06-2023, 12:30 PM   #10
SCerovec
Senior Member
 
Registered: Oct 2006
Location: Cp6uja
Distribution: Slackware on x86 and arm
Posts: 2,474
Blog Entries: 2

Rep: Reputation: 981Reputation: 981Reputation: 981Reputation: 981Reputation: 981Reputation: 981Reputation: 981Reputation: 981
Thumbs up

Quote:
Originally Posted by sndwvs View Post
my board is out of order, so there is no way to test.
source u-boot patches
So sad to hear, is it the PD boot loop or something else?
 
Old 06-06-2023, 12:46 PM   #11
sndwvs
Senior Member
 
Registered: Aug 2014
Posts: 1,915

Original Poster
Rep: Reputation: Disabled
Quote:
Originally Posted by SCerovec View Post
So sad to hear, is it the PD boot loop or something else?
It looks like PD, in maskrom mode the device is found but not flashed. This happened after a power outage.
The main tests will be on orange pi 5 and orange pi 5 plus

Last edited by sndwvs; 06-06-2023 at 12:48 PM.
 
Old 06-06-2023, 01:33 PM   #12
SCerovec
Senior Member
 
Registered: Oct 2006
Location: Cp6uja
Distribution: Slackware on x86 and arm
Posts: 2,474
Blog Entries: 2

Rep: Reputation: 981Reputation: 981Reputation: 981Reputation: 981Reputation: 981Reputation: 981Reputation: 981Reputation: 981
Quote:
Originally Posted by sndwvs View Post
It looks like PD, in maskrom mode the device is found but not flashed. This happened after a power outage.
The main tests will be on orange pi 5 and orange pi 5 plus
Could you make a dumb PSU to type-c cable and try run it off 5 or 12V for testing?
What a pitty
 
Old 06-06-2023, 02:31 PM   #13
sndwvs
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Originally Posted by SCerovec View Post
Could you make a dumb PSU to type-c cable and try run it off 5 or 12V for testing?
What a pitty
I tried, I'll try another type-c cable.
the only bad thing is that I can’t test, otherwise orange pi 5 is currently my desktop with video playback up to 4K.
 
Old 06-06-2023, 03:35 PM   #14
SCerovec
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Quote:
Originally Posted by sndwvs View Post
I tried, I'll try another type-c cable.
the only bad thing is that I can’t test, otherwise orange pi 5 is currently my desktop with video playback up to 4K.
O-Pi5 is breaking the internet indeed, i'd try and get the 32GB hadn't i bought the radxa already...
 
Old 06-07-2023, 09:02 AM   #15
SCerovec
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Quote:
Originally Posted by sndwvs View Post
my board is out of order, so there is no way to test.
source u-boot patches
I tried to build it and it errs out that a clk comparison will always yield true in the build logs?
Am i of so bad luck to run it on a "update & break" day?
 
  


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radxa team, rk3588, rockchip, slackware, slarm64



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