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Powersaving and clock modulation
It is common for laptops to do a reduction in clock frequency when the CPU is idling as to save power.
On different boards I have read that speedstep technology is most useful here. That is, reducing the clock frequency (and often the core voltage) to a lower level as specified by the processor manufacturer. The number of defined frequency/voltage pairs usually ranges from 4 to 6.
I also have read often that the technology which is called clock modulation is hardly useful and doesn't provide and power saving.
I can't understand that. If I look up the specification of clock modulation, it is explained that the clock is being run at nominal frequency and stopped in intervals with a duty cycle between 12.5% and 100%.
Why doesn't that yield any power saving? I always learned that with CMOS semiconductors the clock frequency (i.e. the number of clock transitions) is relevant to determine the power dissipation of a chip.
In my view, if you have a processor running normally at 1000 MHz, it doesn't make any difference whether you let it run on 250 MHz, or use the 1000 MHz clock frequency with a duty cycle of 25%. Note that not the duty cycle of the clock is being varied, but the duty cycle of the clock being run and stopped. The number of clock cycles is then exactly 250 per microsecond.
This does not of course take into account that for clock modulation no voltage reduction is possible.
Still, wouldn't use frequency reduction AND clock modulation yield a better power saving? For example, my Centrino runs on 1.86 GHz, and it throttled down to minimum 800 MHz, and still consumes 13 Watts (shame on Intel!) or so, and keeps the fan running. Why can't I apply a 25% clock duty cycle as to reduce power consumption while the CPU hasn't to do anything better than waiting for my keyboard input?
jlinkels
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