We have connected an Ethernet switch device to Tilera processor using PCI interface. Tilera maps the internal registers of the switch BAR0 and BAR1 memory on its physical address space.

In general BAR0/BAR1 will be mapped in /sys/bus/pci/device/0000:xx:xx.x/resource0 and resource1...
(application accesses and configures the switch, using mmap of resource0/1 .)

Tilera Linux source code arch/tile/asm/pci.h, do not have HAVE_PCI_MMAP defined and does not provide a pci_mmap_page_range function. So in tileGx Linux we are not getting the resource0/1 in /sys/bus/pci/device/0000:xx:xx.x/.

Can someone suggest a different method to access the BAR0/1 in user space using mmap.

Are you aware that support for the tile architecture is about to be dropped ?. Linus has flagged it for the next release he ships.

Yes, I know Linux-4.17 kernel dropping Old CPUs (including tile).
We are using a custom board with Tile processor, and Linux version-3.10.61. There is no planning of Linux upgradation on our custom board at this movement.