LinuxQuestions.org - /sys/class/gpio => Content (B-PI / Android 4.2)

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/sys/class/gpio => Content (B-PI / Android 4.2)

Hello there,

i have a B-Pi with Android 4.2
and i´m exploring the filesystem in sys/class/gpio, because i´m interessted in using IOs

I´m new to linux - i read that everything is represented as files.

I have installed a programm where i can see and open files and wondering, what the directorys and files
are meaning which i see.
in "sys/class/gpio" there are directorys named
gpiochip0
gpiochip24
gpiochip54
gpiochip85
gpiochip119
gpiochip137
gpiochip149
gpiochip167
gpiochip201
gpiochip229
=> what do they mean? Do thier naming have a specific relation to the B-PI´s A20´pins? I can´t match them with the GPIO table from the WIKI / do the numbers have a meaning?
http://wiki.lemaker.org/File""IN_CONNECTOR.jpg

If i go into one of the folders, i see
power (folder)
subsystem (folder)
base (file)
label (file)
ngpio (file)
uevent (file)
=> here also - what do this mean? in power folder there is a file "async" where is just written "disabled", while in folder subsystem the directorys are repeating in a loop

And what is this thing with the "export" and "unexport" files in the gpio folder. I have seen a tutorial on youtube, where these files are used, but i don´t understand thier purpose.

best regards,
Jasson

Quote:

Originally Posted by Jasson (Post 5479277)

I´m new to linux - i read that everything is represented as files.

Not "everything"..
You won't find network devices, e.g. eth0, in /dev.

Quote:

Originally Posted by Jasson (Post 5479277)

... wondering, what the directorys and files
are meaning which i see.
in "sys/class/gpio" there are directorys named
gpiochip0
gpiochip24
gpiochip54
gpiochip85
gpiochip119
gpiochip137
gpiochip149
gpiochip167
gpiochip201
gpiochip229
=> what do they mean?

That is explained in Linux Documentation/gpio/sysfs.txt.

Regards

Ah ok, this clears things up.
I´m still wondering, what the trailing numbers to "gpiochip" are meaning.
Do they refer to the ports of the A20 like PoartA, PortB etc?
For example if i want to turn on PB21
http://wiki.lemaker.org/BananaPro/Pi...ON3_definition
whats the puzzle information i need to identify which "gpiochip(N)" i have to use?

best regards!

Quote:

Originally Posted by Jasson (Post 5481022)

Ah ok, this clears things up.
Im still wondering, what the trailing numbers to "gpiochip" are meaning.

You need to study the Linux documentation better.

Code:

104    /sys/class/gpio/gpiochipN/

105 

106        "base" ... same as N, the first GPIO managed by this chip

Quote:

Originally Posted by Jasson (Post 5481022)

Do they refer to the ports of the A20 like PoartA, PortB etc?

Exactly what "they" are you referring to?
The "N" (what you call a "trailing number") is for a (base) Linux GPIO number.
Normally there's a one-to-one mapping of gpiochipN directories with pin-control (or PIO) control blocks. Each control block is capable of configuring and controlling a group of pins.

But what you have listed for your A20 doesn't match up well with what's in the A20 datasheet and user manual.

Code:

1.19.1. Port Description



The chip has several ports for multi-functional input/out pins. They are shown below:

Port A(PA): 18 input/output port

Port B(PB): 24 input/output port

Port C(PC): 25 input/output port

Port D(PD): 28 input/output port

Port E(PE): 12 input/output port

Port F(PF):  6 input/output port

Port G(PG): 12 input/output port

Port H(PH): 28 input/output port

Port I(PI): 22 input/output port

Typically I would expect the second sysfs gpiochip to be either gpiochip32 (for easy port to chip calculations) or gpiochip18 (to keep the pin numbering consecutive). Instead you report that the second chip is gpiochip24 (which conforms to neither scheme).
You need to obtain the "base" and "ngpio" for each gpiochipN, and try to determine the mapping.

On Atmel SoCs it's easy to map each gpiochipN to its PIO device because the register block address is given in its "label":

Code:

# cat /sys/class/gpio/gpiochip32/label

fffff400.gpio

And the Atmel datasheet indicates that PIOB is located at 0xfffff400. So gpiochip32 (and its pins) maps to PIOB (and its control bits) on this Atmel SoC.

You have to determine the same for your Allwinner SoC. You have an SoC GPIO identified by PIO port letter (i.e. PB) and number (i.e. 21). You have to convert the port letter (PB) to its gpiochipN, and then verify that the PIO number (21) is within the "ngpio" range. The Linux GPIO number to use (for export) is then "base" plus the PIO number.

Regards

Yes, you´re right. I "over-read" a few things the first time. That´s what happens, when you´re doing stuff between 8pm and evening ;>